LSI mainly employs synchronous circuits, in which data in flip-flops is updated in synchronization with the rising edge or the falling edge of a clock signal. Synchronous circuits have an advantage such as the ease of designing, but have a disadvantage of instantaneous increase in power consumption because circuits operate simultaneously in synchronization with a clock signal. Synchronous circuits also have a disadvantage in that the cost for layout design is increased because a clock signal needs to be distributed among components of the circuits without delay.
To eliminate the above disadvantages of synchronous circuits, asynchronous circuits are employed, in which data is transmitted and received between circuit portions without using a clock signal by a method called “handshake.” As a communication protocol for asynchronous circuits, a four-phase dual-rail protocol is known, in which dual-rail encoding and four-phase encoding are used in combination (see Patent Document 1).
The four-phase dual-rail protocol will be described with reference to FIGS. 22A to 22C.
FIG. 22A is a block diagram showing the concept of the four-phase dual-rail protocol. As shown in FIG. 22A, data is communicated by two signal lines x and y. A sender sends data to a receiver. In response to a request (req) from the sender, the receiver sends back an acknowledgement signal (ack) to the sender to signify the receipt of the data.
FIG. 22B shows a truth table of the four-phase dual-rail protocol. In dual-rail encoding, 1-bit data is expressed using two signal lines. A state where (x, y)=(1, 0) means that data is “0.” A state where (x, y)=(0, 1) means that data is “1.” A state where (x, y)=(0, 0) is called “spacer” that is used to delimit consecutive data. A state where (x, y)=(1, 1) is called “inhibit” that is an invalid value which a circuit cannot have according to the operating principle.
FIG. 22C is a timing chart showing a communication procedure for the four-phase dual-rail protocol. In the four-phase dual-rail protocol, data (“0” or “1”) and a spacer are alternately exchanged. First, the sender identifies an acknowledgement signal from the receiver and sends data to the receiver (1). In FIG. 22C, data “0” is sent as an example. Next, the receiver detects the data and sends an acknowledgement signal to the sender (2). Then, the sender identifies the acknowledgement signal and sends a spacer to the receiver (3). The receiver detects the spacer and sends an acknowledgement signal to the sender (4). In such a manner, the four-phase dual-rail protocol requires four steps to complete one data transfer.
A transistor using an oxide semiconductor or a metal oxide in its channel formation region (an oxide semiconductor transistor, hereinafter referred to as OS transistor) exhibits an extremely low off-state current. Patent Document 2 discloses a flip-flop capable of storing a logic state even while power supply is stopped, by using an OS transistor with the extremely low off-state current.